1. Field of the Invention
The present invention relates to information handling systems and more particularly to electronic information handling peripheral subsystems having a cache storage and a backing storage and control means for controlling read and write access to records in the cache and in the backing store.
There is a group of users of information handling systems which require a very high number of transactions per second. This group has a clear need for fast access to data, reliable storage of data, efficient Direct Access Storage Devices (DASD), a high message processing rate, balanced activity between DASD actuators, and tailored hardware and software. These installations have average DASD I/O rates ranging from 500 to over 13,500 transactions per second. These users are typically found in the airline, financial, hotel, and data service industries. Their requirements make them sensitive to service times and use of DASD storage.
The present invention is especially adapted to satisfy these users' present and future needs. Using cache technology, it supplies fast and reliable access to data and provides more efficient use of DASD storage.
2. Description of the Prior Art
The following are systems representative of the known prior art.
Peripheral data-storage hierarchies have been used for years for providing an apparent store as suggested by Eden, et al in U.S. Pat. No. 3,569,938. Eden, et al teach that in a demand paging or request system, chaching data in a cache-type high-speed front store (buffer) can make a peripheral storage system appear to have a large capacity, yet provide fast access to data; fast access being faster than that provided by the back store. Eden, et al also teach that the back store can be a retentive store, such as magnetic tape recorders and magnetic disk recorders (direct access storage devices or DASD), while the front store can be a volatile store, such as a magnetic core store. With the advances in data storage technology, the front store typically includes semiconductive-type data storage elements. U.S. Pat. No. 3,839,704 shows another form of such a data storage hierarchy.
An important aspect of data storage hierarchies is enabling data integrity. That is, the data received from the user, such as a central processing unit (CPU) or other data handling device, should be returned to the supplying unit either correct or with an indication that errors may exist. Also, it is typical practice in data storage hierarchies to automatically move data from a higher level to a lower level for retentive storage as well as limiting the data in the higher levels such that other data can be stored for fast access. U.S. Pat. No. 4,020,466 shows copying changes from a high-level store to a backing store, while U.S. Pat. No. 4,077,059 shows forcing copyback under predetermined conditions. Such copyback operations can consume data storage hierarchy time, i.e., so much data may be copied badk that access to the data by a using unit may be degraded. This problem is partially solved by U.S. Pat. No. 3,588,839 which teaches that the only data that need be copied back from a high-level storage unit to a low-level storage unit is that data that is altered, i.e., where there is noncongruence between data in a backing store and data in a front store.
Data storage hierarchies have taken diverse forms. For example, in accordance with the Eden, et al patent 3,569,938 a single high-speed store serviced several users. U.S. Pat. No. 3,735,360 shows that each processor can have its own high-speed store, or cache, for different performance reasons. Performance of the data storage hierarchies also is affected by the algorithms and other controls used to place predetermined data into the cache front store, or high-speed (fast access) storage portion. Accordingly, U.S. Pat. No. 3,898,624 shows that varying the time of fetching data from a backing store to a front, or caching store can be selected by a computer operator in accordance with the programs being executed in a CPU. In this manner, it is hoped that the data resident in the cache, or upper level of the hierarchy, will be that data needed by the CPU while other data not needed is not resident. All of these operations become quite intricate.
Accordingly, evaluation programs have been used to evaluate how best to manage a data storage hierarchy. U.S. Pat. Nos. 3,964,028 and 4,068,304 show performance monitoring of data storage hierarchies for enhancing optimum performance while ensuring data integrity. Much of the work with respect to data storage hierarchies has occurred in the cache and main memory combinations connected to a CPU. The principles and teachings from a cached main memory relate directly to caching and buffering peripheral systems, as originally suggested by Eden, et al, supra. Of course, main memory has been used prior to Eden, et al for buffering or caching data from a magnetic tape and disk unit for a CPU, i.e., a main memory was not only used as a CPU working store but also as a buffer for peripheral devices. To enhance access to data, some data is "pinned" or "bound" to the front store; that is, a copy of such data is guaranteed to be kept in the front store while other data is subject to replacement by new data based upon usage characteristics. Unless such pinned data is copies to a retentive store, a significant data integrity exposure exists.
The performance monitoring referred to above indicates that it is not always in the best interests of total data processing performance and integrity to always use a caching buffer interposed between a using unit and a backing store. For example, U.S. Pat. No. 4,075,686 teaches that a cache can be turned on and off by special instructions for selectively bypassing the cache. Further, the backing store or memory can be segmented into logical devices with some of the logical devices, or segments, being selectively bypassed, such as for serial or sequential input-output operations. This patent further teaches that, for certain commands, it is more desirable to not use cache than to use cache. U.S. Pat. No. 4,268,907 further teaches that for a command specifying the fetching of data words an indicator flag is set to a predetermined state. To prevent replacement of extensive numbers of data instructions already stored in cache during the execution of such instructions, such flag conditions replacement circuits to respond to subsequent predetermined commands to bypass cache storage for subsequently fetched data words. U.S. Pat. No. 4,189,770 shows bypassing a cache for operand data while using cache for instruction data.
In newer designs, the storage capacity of the front store tends to increase. Such increased capacity is often accompanied with faster I/O channel rates, which in turn place increased demands on which data is stored in the front store. Such changes mean that more and more data is stored in the front store. This increased data storage in a volatile front store aggravates a data integrity problem which may be caused by power supply perturbations or outages, for example. Integrity can be ensured by always recording the data in a retentive back store. This requirement tends to degrade performance, i.e., increases data access times. Selective retentive journalling of data as suggested by C. E. Hoff, et al in IBM TECHNICAL DISCLOSURE BULLETIN article "Selective Journalling", June 1975, Vol. 18 No. 1, pages 61-2, reduces performance degradation but does not control the data integrity exposure in a completely satisfactory manner. In a similar vein, Campbell, et al in the IMB TECHNICAL DISCLOSURE BULLETIN, Vol. 18 No. 10, March 1976, pages 3307-9 show multiple replacement classes in a replacement control for limiting interlevel transfers in a multi-level hierarchy. Such techniques still leave a large data integrity exposure or provide limited performance.
A peripheral data storage system's operation-completion indication to a host processor is usually a DEVICE END signal; the DEVICE END indicates that the data received from the host is retentively stored in the data storage system.
U.S. Pat. No. 4,410,942 shows a tape data recorder system including a volatile data buffer having plural modes of operation. In a preferred mode, termed "tape buffer mode", the above-described DEVICE END signal is supplied to the host processor when the data is stored in the volatile buffer but not yet stored in the retentive-storing tape recorder. The data is stored in a tape recorder after the DEVICE END signal. A separate SYNCHRONIZE command from the host to the data storage system requires that all data stored in the volatile buffer be then stored in the tape recorder. In other modes of operation of the volatile buffer, the DEVICE END signal is only sent to the host after the data is stored in the retentive tape recorder. The data storage system also honors a command READ DATA BUFFER which transfers data stored in the buffer (whether sent to the buffer by the host or by a tape recorder) to the host. When data is sent by a host to the data storage system, such data is always intended to be and will be recorded in a retentive tape recorder, as indicated above. The READ DATA BUFFER involves an error recovery technique; usually there is no way of retrieving the data in buffer that was received from the host for a write-to-tape operation.
A possible solution to the data integrity exposure is to provide a retentive front store, such as used in the IBM 3850 Mass Storage System. There DASDs are the cache, or front store, while magnetic tape is a back store. A simplified showing of this type of data storage hierarchy is found in the article by Blickenstaff, et al "Multilevel Store Directory Integrity", IBM TECHNICAL DISCLOSURE BULLETIN, Vol. 20 No. 3, August 1977, pages 939-940. Unfortunately, such retentive buffer usually does not provide the performance (short data access times) sometimes demanded by present-day computers. Accordingly, for a truly high-performance data storage hierarchy, some means must be found to use a large volatile front store while controlling the attendant data integrity exposures. This exposure control also applies to other systems such as printing, communications, and the like.
IBM TECHNICAL DISCLOSURE BULLETIN, Vol. 21 No. 1, June 1978, page 280 describes a mechanism for reducing cache deadlock probability on a store-end-cache multiprocessor having hardware control check pointing without incurring degradation.
IBM TECHNICAL DISCLOSURE BULLETIN, Vol. 18 No. 8, January 1976, page 2643 describes a method for selectively copying portions of a data base normally stored in a memory subsystem portion of a data processing system.
IBM TECHNICAL DISCLOSURE BULLETIN, Vol. 20 No. 5, October 1977, page 1955 describes a check point copy operation for a two-stage data storage facility.